Through silicon vias (TSVs) are used to carry high frequency signals in three-dimensional integrated circuit (IC) technology. As opposed to back end of line (BEOL) wires, the TSV signal is very close to the silicon substrate and is expected to induce significant noise coupling into the circuits. Extremely thin silicon-on-insulator (ETSOI) devices show an even greater impact from TSV high frequency noise due to the ETSOI devices having a fully depleted channel.
Several solutions have been proposed to mitigate the noise coupling. One solution includes using large keep out zones (KOZs). However coupling is seen even when the keep out zone is large (e.g., an 80 micrometer (μm) or greater keep out zone) and there is a layout area penalty.
Another solution that has been proposed to mitigate the noise coupling is to use a thicker dielectric surrounding the TSVs. However, it is difficult in practice to form a thick dielectric layer. Thus, process flows involving a thicker dielectric result in integration challenges and decrease production yield.
Therefore, techniques for reducing the noise coupling from TSVs in ETSOI device designs without area penalty would be desirable.